Samsung has initiated shipments of its HBM4 memory to customers and has announced the commencement of mass production of this cutting-edge technology.
The HBM4 chips are manufactured using a 6th generation 10nm-class DRAM process known as “1c.” It is important to note that DRAM architecture differs from CPU cores, and thus the technology nodes are not directly comparable. The HBM4 products also incorporate a 4nm logic base die to enhance performance.
For context, HBM4 is capable of achieving speeds of 11.7Gbps per pin, which exceeds the industry standard of 8Gbps by 46%. With 2,048 pins, the total bandwidth reaches an impressive 3.3 terabytes per second, signifying a notable 2.7x increase over HBM3E.
JEDEC, the governing body for computer RAM, opted to standardize HBM4 with a lower per-pin bandwidth compared to HBM3E (9.6Gbps). However, the number of pins was doubled from 1,024 to 2,048, aiming for improved power efficiency and enhanced thermal management.
Samsung has successfully surpassed its target per-pin speed for HBM4 and outperformed the previous HBM3E speed. The company anticipates that future developments may yield chips capable of reaching 13Gbps per pin.
At present, Samsung’s HBM4 memory utilizes a 12-layer stacking technology, offered in capacities ranging from 24GB to 36GB. The company is prepared to respond to customer needs and may introduce a 16-layer design with capacities up to 48GB.
The Samsung-designed HBM4 memory features low-voltage through-silicon vias and an optimized power distribution network, resulting in a 40% improvement in power efficiency. Additionally, the memory stack boasts 10% lower heat resistance and 30% better heat dissipation compared to HBM3E.
Samsung is forecasting substantial demand for its memory products in 2026, predicting that sales will triple compared to 2025. In light of this, the company is actively working to expand its HBM4 production capacity.
Looking ahead, Samsung plans to sample next-generation HBM4E memory to customers in the latter half of 2026. In 2025, it will provide custom HBM samples tailored to client specifications.
“Instead of following the traditional path of using existing proven designs, Samsung embraced a pioneering approach by adopting advanced nodes such as the 1c DRAM and 4nm logic process for HBM4. By leveraging our process competitiveness and design optimization, we can secure substantial performance headroom, fulfilling our customers’ growing demands for higher performance as needed,” stated Sang Joon Hwang, Executive Vice President and Head of Memory Development at Samsung Electronics.
Source
